1. Field of the Invention
The present invention relates to switching power supply circuitry which employs current mode control to achieve output voltage regulation. More specifically, the invention relates to DC-to-DC converters which include a current mode switching controller or regulator (implemented as an integrated circuit, including an oscillator which produces a ramped voltage which periodically increases at a fixed ramp rate), circuitry (including a current sense resistor) external to the integrated circuit controller or regulator, and ramp adjustment circuitry (including an element external to the integrated circuit) which sets the effective ramp rate of the oscillator's ramped voltage.
2. Description of the Related Art
FIG. 1 is a conventional DC-to-DC converter which includes current mode switching controller 1 which is implemented as an integrated circuit (chip), and boost converter circuitry which is external to controller chip 1. The boost converter circuitry comprises NMOS transistor N1 (which functions as a power switch), inductor L, current sense resistor R.sub.s, Schottky diode D, capacitor C.sub.out, feedback resistor divider R.sub.F1 and R.sub.F2, compensation resistor R.sub.c, and compensation capacitor C.sub.c, connected as shown. The FIG. 1 circuit produces a regulated DC output voltage V.sub.out across load R.sub.o, in response to input DC voltage V.sub.in.
Controller chip 1 includes oscillator 2 (having a first output and a second output), comparator 8, driver 6 which produces an output potential V.sub.DR at pad 12 (to which the gate of switch N1 is coupled), latch 4 (having "set" terminal coupled to oscillator 2, "reset" terminal coupled to the output of comparator 8, and an output coupled to the input of driver 6), error amplifier 10 (having a non-inverting input maintained at reference potential V.sub.ref), and circuit 9 (having a first input coupled to the second output of oscillator 2, a second input coupled to pad 13, and an output coupled to the inverting input of comparator 8).
Pad 13 is at potential V.sub.c, which is determined by the output of error amplifier 10 (in turn determined by the difference between the instantaneous potential at Node A and the reference potential V.sub.ref) and the values of external resistor R.sub.c and capacitor C.sub.c. Reference potential V.sub.ref is set (in a well known manner) by circuitry within chip 1, and is normally not varied during use of the circuit. In order to set (or vary) the regulated level of the output voltage V.sub.out, resistors R.sub.F1 and R.sub.F2 with the appropriate resistance ratio R.sub.F1 /R.sub.F2 are employed.
Oscillator 2 asserts a clock pulse train (having fixed frequency and waveform as indicated) at its first output, and each positive-going leading edge of this pulse train sets latch 4. Each time latch 4 is set, the potential V.sub.DR asserted by driver 6 to the gate of transistor N1 causes transistor N1 to turn on, which in turn causes current I.sub.L from the source of N1 to increase in ramped fashion (more specifically, the current I.sub.L increases as a ramp when transistor N1 is on, and is zero when transistor N1 is off. The current through diode D is zero when N1 is on, it increases sharply when N1 switches from on to off, then falls as a ramp while N1 is off, and then decreases sharply to zero when N1 switches from off to on). Although transistor N1 turns on at times in phase with the periodic clock pulse train, it turns off at times (which depend on the relation between reference potential V.sub.ref and the instantaneous potential at Node A) that have arbitrary phase relative to the pulses of the periodic clock pulse train.
Oscillator 2 asserts ramped voltage V.sub.osc (which periodically increases at a fixed ramp rate and then decreases, with a waveform as indicated) at its second output. Circuit 9 asserts the potential V.sub.c -V.sub.osc to the inverting input of comparator 8. Assertion of the potential V.sub.c -V.sub.osc (rather than V.sub.c) to comparator 8 is necessary for stability.
The non-inverting input of comparator 8 is at potential V.sub.s =I.sub.L R.sub.s, which increases in ramped fashion in response to each "set" of latch 4 by oscillator 2. When V.sub.s =V.sub.c -V.sub.osc (after latch 4 has been set), the output of comparator 8 resets latch 4, which in turn causes the potential V.sub.DR asserted by driver 6 to the gate of transistor N1 to turn off transistor N1. Thus, by the described use of both of the signals output from oscillator 2, and feedback asserted to error amplifier 10 from Node A, controller chip 1 switches transistor N1 on and off with timing that regulates the output potential V.sub.out of the FIG. 1 circuit.
However, the conventional circuit of FIG. 1 has an important disadvantage. Although the ramp rate of the oscillator output V.sub.osc is fixed, the optimal value of this rate varies from application to application and depends on the particular implementation of the circuitry external to controller chip 1 (the optimal oscillator ramp rate depends on a number of parameters including the level of input potential V.sub.in and the inductance of inductor L). Thus, since the ramp rate of the oscillator output V.sub.osc is fixed, it is difficult to implement the FIG. 1 circuit so as to be stable for use with a wide range of values of input potential V.sub.in, and with an acceptably wide range of characteristics of its external circuit components (such as the inductance of inductor L).
The inventor has recognized that it would be desirable to improve the FIG. 1 circuit so that the effective ramp rate of the oscillator output V.sub.osc is variable. The inventor has also recognized that it would be desirable to so improve the FIG. 1 circuit without increasing the number of external pins to the controller chip of the improved circuit.
Other conventional DC-to-DC converters include a current mode switching controller implemented as an integrated circuit (as does the FIG. 1 circuit), but also include circuitry (e.g., buck converter circuitry) other than boost converter circuitry that is external to the controller chip. The circuitry external to the controller chip includes a current sense resistor, and the controller chip includes an oscillator which produces a ramped voltage which periodically increases at a fixed ramp rate. This class of conventional converters is also subject to the above-noted disadvantage of the FIG. 1 circuit.
We shall use the expression "current mode switching regulator" chip herein to denote a circuit which performs the functions of a "current mode switching controller" chip (e.g., controller 1 of FIG. 1) but which also includes an on-board power switch. In contrast, a "current mode switching controller" chip does not include an on-board power switch and must be used with an external power switch (e.g., controller chip 1 of FIG. 1 is used with NMOS transistor N1 which is external to controller chip 1).
Another type of conventional DC-to-DC converter differs from the FIG. 1 circuit (or the above-mentioned variations thereon) in that the current mode switching controller chip is replaced by a current mode switching regulator chip. The current mode switching regulator chip in each such converter does not include a sense resistor, and instead is used with an external sense resistor (such as resistor R.sub.s of FIG. 1). For example, one such converter employs a current mode switching regulator chip that differs from chip 1 of FIG. 1 in that counterparts to NMOS transistor N1 and resistors R.sub.f1 and R.sub.f2 are implemented on-board the regulator chip. In this latter type of converter, the circuitry that is external to the regulator chip does not include an external power switch, but it does include an external sense resistor (e.g., an external sense resistor identical to resistor R.sub.s of FIG. 1). This class of conventional converters is also subject to the above-noted disadvantage of the FIG. 1 circuit.